1. Field of the Invention
The present invention related generally to the fabrication of semiconductor pixel imager arrays, and more particularly, to a novel semiconductor pixel imager structure and novel process therefor for increasing the sensitivity of the optical image sensors by optimizing the dielectric layer under the lenses.
2. Description of the Prior Art
CMOS image sensors are beginning to replace conventional CCD sensors for applications requiring image pick-up such as digital cameras, cellular phones, PDA (personal digital assistant), personal computers, and the like. Advantageously, CMOS image sensors are fabricated by applying present CMOS fabricating process for semiconductor devices such as photodiodes or the like, at low costs. Furthermore, CMOS image sensors can be operated by a single power supply so that the power consumption for that can be restrained lower than that of CCD sensors, and further, CMOS logic circuits and like logic processing devices are easily integrated in the sensor chip and therefore the CMOS image sensors can be miniaturized.
The patent literature is replete with references describing CMOS image sensor arrays and aspects of their manufacture. United States Patent Publication Nos. 2003/0038293, 2002/0033492 and 2001/0010952 describe typical state of the art CMOS image array designs, as do issued U.S. Pat. Nos. 6,635,912, 6,611,013 and 6,362,498. However, none of these state of the art devices described utilize Copper metallization layers in the pixel design. That is, AlCu metal levels are currently fabricated in current CMOS image sensors that require a thicker dielectric stack due to the increased resistivity of the Al metal. The thicker the dielectric means thicker interlevel dielectric layers are required which results in a reduced intensity of light that reaches the pixel photoconversion element (e.g., photodiode). Thus, the sensitivity of the CMOS imager pixel is compromised.
As the semiconductor industry is expected to stay with AlCu for 0.18 μm node CMOS image sensor technology, it would be highly desirable to provide a CMOS image sensor having damascene Copper (Cu) metal lines for the metallization (e.g., M1, M2) levels which would require a thinner interlevel dielectric stack which has less thickness variability due to the elimination of the dielectric CMP step required with subtractive etch AlCu wiring, thus increasing the sensitivity of the pixel array as more light will reach the photodiode. However, as passivation levels is required on Cu metals due to Copper's susceptibility to oxidation and contamination, a SiN, SiC, SiCN or like passivation layer is required above the copper wires. That is, SiN, SiC, SiCN or like layers used for damascene copper wiring as RIE stop and Cu diffusion barriers are not compatible with optical image sensors due to refractive index mismatch issues.
It would thus be highly desirable to provide a CMOS image sensor and method of manufacture wherein the sensor comprises Copper (Cu) metal lines for the metallization levels which resolves the refractive index mismatch issues and, at the same time, optionally increase the sensitivity of the optical image sensors by optimizing the dielectric layer under the lenses.